An analog output waveform generated by a DAC is ideally a linear function of a digital code appearing at the DAC input (“DAC code”). Indeed, the degree of linearity between the digital input and the analog output is considered to be a quality of merit of the DAC. Non-linearities in a DAC output may adversely affect applications utilizing the DAC. For robotics applications, for example, non-linearities in a DAC output may cause jerkiness in fine movements that could negatively impact the function being performed by a robotic device.
To illustrate two common forms of DAC non-linearity, the reader is invited to imagine a sequence of adjacent DAC codes presented at the input to a DAC. “Adjacent DAC codes” in this context means two codes representing the smallest analog output step that the DAC is designed for. For example, in the case of an 8-bit DAC with a binary input, 28=256 output levels may be created. Such a DAC may be designed with a 2.56 volt upper supply rail such that the input DAC code 00000000 corresponds to an analog output of zero volts and the input DAC code 11111111 corresponds to an analog output of 2.55 volts. It is noted that some DACs may be designed such that the output voltage associated with the largest binary input code is one least significant bit (“LSB”) voltage step lower than the magnitude of the upper supply voltage rail. Doing so provides for 2N output voltage levels and 2N−1 steps beginning with 0.0 volts. Each level corresponds to one of the 2N combinations associated with the N-bit wide DAC input word. The voltage difference corresponding to adjacent DAC codes in such case is (2.56 volts/256 output levels)=0.01 volts. Sequentially presenting adjacent DAC codes of 00000000 and 0000001, for example, ideally result in a DAC output voltage step from 0.00 volts to 0.01 volts.
A magnitude vs. time waveform appearing at the output of the example DAC in response to the imagined sequence of increasing adjacent DAC codes is stair-stepped. Each step represents an increase in magnitude of the output quantity (e.g., typically voltage or current) that is equal to the increase in magnitude of the previous level. Differential non-linearity (“DNL”) is defined as the difference between a measured step magnitude associated with adjacent DAC codes and the ideal (calculated) step magnitude associated with the same adjacent DAC codes. DNL is a measure of a DAC's resolution. A second measure of real-world and ideal DAC linearity is integral non-linearity (“INL”). INL is defined as the difference between the measured output level for a given DAC code and the ideal (calculated) output level for that same DAC code. INL is a measure of DAC accuracy and may be thought of as a summation of DNL non-linearities over some arbitrary sequence of adjacent DAC codes.
One skilled in the art will understand that modern DACs are commonly implemented by integrating matched-resistance switched resistor voltage divider networks as further described below. One source of DNL and INL non-linearities is the mismatching of resistors in the networks due to semiconductor process imperfections. Mismatching occurs as resistors are reduced in size such that the area occupied by a resistor becomes closer in size to the process width. Such “closely located” mismatching between two resistors is inversely proportional to the square root of the area occupied by each resistor. Accordingly, closely-located mismatching may be reduced by increasing the area occupied by a resistor in a DAC voltage divider resistor network. Doing so may easily be accomplished by proportionally increasing both the width and length of the resistive material in order to maintain a constant resistance.
As used herein, the term “1 UW” means one “unit-width” and is a process-dependent base width such as the process width. For example, a 1 UW resistor of a nominal resistance value R implemented with a width equal to the process width for a one micron process has a path width of one micron. It is not necessary that the base width be equal to the process width, however. A 1 UW resistor may, for example, be implemented with a path width of two microns using a one micron process. Multi-width resistors as referred to herein have a path width that is an integer multiple of the base width. For example, a 2 UW resistor of resistance R has a path width that is twice the path width of a 1 UW resistor of resistance R. The example 2 UW resistor also has twice the length of the 1 UW resistor in order to maintain the resistance constant at R. It is noted that the 2 UW resistor described occupies four times the area of the 1 UW resistor, given that both the width and the length must double in order to maintain a constant resistance R. Likewise, a 4 UW resistor is four times as wide and four times a long as a 1 UW resistor and occupies 16 times the area of the 1 UW resistor. It is also noted that resistor area may be increased by increasing the width and length of a single resistor of resistance R or by implementing a serial/parallel matrix of 1 UW resistors whose total resistance is equal to R. It is noted that, as used hereinafter and as illustrated on schematic diagrams associated with this application, the symbol “R” is used to indicate a resistor having a nominal resistance equal to R. However, the resistor R may be fabricated from a series/parallel network of resistors, each of the latter also having a nominal resistance value of R.
FIG. 1A is a prior-art schematic diagram illustrating a 2 UW resistor 102 implemented with a serial/parallel matrix 104 of four unit-width resistors 105, 110, 115, and 120. Each of the resistors 105, 110, 115, and 120 has a resistance R; and the equivalent resistance of the matrix 104 has a total resistance of R. The total area equals four times the area of a single UW resistor and is thus more costly in terms of semiconductor materials and process costs. The advantage of implementing a resistor using such a matrix, though, is that the resistor has double the closely-located matching capability of a single 1 UW resistor R.
FIG. 1B is a prior-art schematic diagram illustrating a 4 UW resistor 140 implemented with a serial/parallel matrix 150 of 16 unit-width resistors. Each of the sixteen single UW resistors has a resistance R, and the equivalent resistance of the matrix 150 has a total resistance of R. The total area equals sixteen times the area of a single UW resistor and has four times the closely-located matching capability of a single 1 UW resistor R. Resistors with a width of 8 UW, 16 UW, 32 UW, etc. may be implemented in a similar way. Each such expanded area resistor occupies an area that is a squared function of the UW multiplier and decreases the closely-located matching error by a factor equal to the UW multiplier. In summary, the resistor closely-located matching error σ∝
      1                  W        ⁢                                  ⁢        L              ,where W and L are the width and length of the resistors. The resistors are sized to meet a selected circuit accuracy.
One problem with increasing resistor area to decrease closely-located mismatch is an increase of the so-called “long-distance mismatch” error which contributes to DNL and INL non-linearities. Components of long-distance mismatch are wafer gradients, stress gradients, and thermal gradients. The term “wafer gradient” refers to a non-uniformity of thickness across a semiconductor area of interest. Resistance values of semiconductor implemented resistors are a function of the width, length and thickness of the material (e.g., polysilicon) used to implement the resistor. Wafer gradients result in a resistance mismatch between resistors implemented across increasingly larger areas. Stress gradients may occur during semiconductor bonding and packaging processes and may result in resistance differences between resistors implemented across increasingly larger areas. Thermal gradients result from thermal emissions during device operation and may also result in resistance differences between resistors implemented across increasingly larger areas. Thus it can be seen that decreasing closely-located mismatch by increasing the area occupied by one or more resistors increases long-distance mismatch.
FIG. 2 is a prior-art schematic diagram of an example segmented resistor DAC 200. The DAC 200 is described in U.S. Pat. No. 8,013,772 B2, incorporated herein by reference in its entirety. The DAC 200 is an example of a state-of-the-art compromise between increasing resistor area in certain portions of the DAC to decrease closely-located mismatch and decreasing resistor area in other portions of the DAC to decrease long-distance mismatch. The DAC 200 utilizes a binary weighted “R-2R” resistor ladder architecture for the least significant bits (“LSBs”) (e.g., bits 0-9 in this example case) for a binary portion 210 of the overall resistor ladder. The DAC 200 utilizes an equally weighted resistor ladder architecture for the most significant bits (“MSBs”) (e.g., bits 10 and 11 in this example case) of a linear portion 215 of the overall resistor ladder.
For the binary R-2R portion 210 of the DAC 200, each double resistance “rung” of the resistor ladder (e.g., the rung 218 including the resistors 219 and 220) in the case of bit<7>220) is connected between an intermediate node (e.g., the node NN7 222) and a switching node (e.g., the switching node N7 225. A single-R resistor (e.g., the resistor 228) is coupled between each intermediate node (e.g., the node NN7 222) and the next higher-order node (e.g., the node NN8 232).
The state of each bit of a DAC binary input word 235 determines which of two voltage levels the switching node of the corresponding double-resistance rung of the resistor ladder is switched to. For example, an active state of bit <7>220 switches the node N7 225 of the rung 218 to a voltage rail RV_TOP 236 of voltage V_TOP. An inactive state of bit<7> switches the rung 218 to a ground voltage rail RV_GND 240 of voltage V_GND. The above-described R-2R architecture results in each successively higher-order rung contributing double the DAC output voltage V_DAC_OUT (also referred to herein as the “weight”) as the previous lower-order rung to a DAC analog output terminal DAC_OUT 243. The R-2R binary portion 210 of the resistor ladder DAC 200 is thus directly compatible with the binary numbering system. Each bit of the binary input word 235 switches a corresponding R-2R ladder rung to RV_TOP 236 when the bit goes active, causing the intermediate node voltage associated with the ladder rung to contribute to the output voltage V_DAC_OUT at the output terminal DAC_OUT 243. Likewise, an inactive bit switches the ladder rung to RV_GND 240 to remove the ladder rung voltage contribution from DAC_OUT 243.
It is noted that, for the example DAC 200, the series 2R combination of the lowest-order resistors 244 and 245 are permanently coupled to RV_GND 240. Doing so enables the DAC to operate properly for all input words and limits the maximum output voltage of the DAC 200 to the voltage V_TOP of the rail RV_TOP 236 minus (V_TOP/2N).
In contrast, the term “linear architecture,” referring to the linear portion 215, means that each branch of the linear portion 215 (e.g., the branch 248 consisting of resistors 249 and 250) is connected to the DAC_OUT terminal 243 and is switched between DAC_OUT 243 and either RV_TOP 236 (“active”) or RV_GND 240 (“inactive”). As such, each active branch of the linear portion contributes to the output voltage at DAC_OUT 243 by an amount equal to that of each of the other active branches of the linear portion 215. Also, each active linear branch contributes a percentage of the output voltage equal to the percentage contributed by the entire binary portion when all branches of the binary portion are active (all binary portion branches connected to RV_TOP 236).
Branches of the linear portion 215 are not switched directly by bits of the binary input word 235 as a consequence of being equally weighted and not binary weighted. Rather, a binary to thermometer decoder 253 decodes bits 10 and 11 in order to switch each of the linear branches 248, 257 and 260 between RV_TOP 236 and RV_GND 240 as the states of bits 10 and 11 change. Doing so causes each of the branches 248, 257 and 260 to contribute an equal percentage of the output voltage at DAC_OUT 243 when all three linear branches are switched to RV_TOP 236.
Said differently, the binary portion 210 of the DAC 200 and each of the linear branches 248, 257 and 260 contribute 25% of the output voltage at DAC_OUT 243 when input bits [0:11] are all set. It is noted that the total bit width of the input word 235 and the number of bits implemented in the binary portion 210 vs. the number of bits implemented in the linear portion 215 of the example segmented resistor ladder DAC 200 are merely examples and may vary from one implementation to another without altering the essence of the description herein.
The DAC 200 represents a compromise between increasing resistor area in certain portions of the DAC to decrease closely-located mismatch and decreasing resistor area in other portions of the DAC to decrease long-distance mismatch, as previously mentioned. Areas of resistive material used to implement resistive rungs of the binary portion 210 are upwardly scaled in binary fashion for successively higher-order bits beginning at a chosen bit level. Thus, for example, the rung resistors associated with bit 0-5 may be fabricated at 1 UW, bit 6 at 2 UW, bit 7 at 4 UW, bit 8 at 8 UW and so on. 1 UW is generally the minimum material width allowed for a given fabrication process. The resistor areas, a squared function of the UW factor as shown in FIGS. 1A and 1B, are scaled upward to reduce closely-located mismatch error. The scaling is done in accordance with the contribution of the bit weight of a particular branch to the overall output voltage and thus to the overall closely-located mismatch error. This is done conservatively and in a bit-weight scaled fashion (rather than simply scaling all ladder resistor areas upward by a factor appropriate to the highest-order bit) in order to avoid undue increases in long-distance mismatch caused by the area increases.
The highest-order resistor 265 of the binary portion 210 of the example DAC 200 is scaled at 32 UW. Doing so limits the closely-located mismatch error of the highest-order branch of the binary portion 210 to a selected range matching that of lower-order branches. Each of the three branches 248, 257 and 260 of the linear portion 215 has the same influence on the output voltage as the binary portion 210, as previously mentioned. Therefor, it is desirable that the closely-located mismatch error of each linear branch 248, 257 and 260 be within the same excursion as that of the binary portion 210. Consequently, the branch resistors of the linear portion branches 248, 257 and 260 may each be scaled at 32 UW to maintain closely-located mismatch equivalency with the binary portion 210. If implemented with R-2R architecture, the bit 10 rung and inter-nodal resistors would be fabricated as 32 UW resistors. The bit 11 rung and inter-nodal resistors would be fabricated as 64 UW resistors. Taking into account the number of resistors of each UW and the UW squaring factor for an R-2R vs. a linear implementation of bits 10 and 11, the example segmented binary/linear DAC 200 consumes only one-half the area of a full binary 12-bit R-2R DAC. The aforesaid techniques of resistor size up-scaling and segmentation between binary and linear portions of the resistor divider networks associated with the example DAC 200 thus reduce total silicon area without increasing closely-located and long-distance mismatch error and negatively affecting DNL performance.
Taking the segmentation idea a step further, semiconductor area may be further reduced by implementing three MSBs (bits <11:9>) as seven linear branches, leaving the binary portion limited to nine R-2R branches to implement LSB bits <8:0>. However, doing so would increase the layout difficulty of locating paired objects next to each other. That is because the number of matched object pairs would increase from 6 (two-object combinations from three linear branches plus one binary portion) to 28 (two-object combinations from seven linear branches plus one binary portion).